The present invention relates generally to complementary insulated gate field effect transistor (IGFET) amplifiers and more particularly to complementary IGFET amplifiers with emitter follower outputs.
One of the major design criterion of semiconductor circuits is that individual circuit elements be small to enable high packing density as well as consume small amounts of power. Complementary IGFETs consume smaller amounts of power and have higher switching speeds than other types of semiconductor structures. By reducing the size of the IGFET device, the on resistance becomes high. When the load to the output stage is capacitive, the switching speed becomes unsatisfactorily low.
The output structure of IGFET buffers generally consist of large P channel and N channel devices to provide reasonable drive and sink capabilities. Typically, a P channel pull-up device is 300 times an internal minimum size device and a typical N channel pull-down device is 200 times a internal minimum size device.
Instead of increasing the size of the output stage IGFETs, the prior art has incorporated bipolar devices in the output stage. A typical example is U.S. Pat. No. 3,636,372 to Hujita, et al when includes a transistor and an emitter-follower configuration and a load impedance or resistance in series with the emitter. As illustrated in FIG. 1, the input inverter includes a complementary pair of insulated gate field effect transistors Q.sub.1 and Q.sub.2 connected in an inverter structure. The output stage includes a bipolar transistor Q.sub.3 connected to the output of the inverter with a load resistance RE and an output capacitance C.sub.out connected to the emitter. With this configuration, although improving drive capacity with a minimum amount of space or surface area used, the achievable speed is dictated by the output resistance and substantial power is consumed. Also, the maximum achievable output voltage is the supply voltage minus one base to emitter diode voltage drop (V.sub.CC -V.sub.BE). Assuming a typical output capacitance of 100 picofarads and an output load resistance of approximately 100 ohms in order to provide a high to low transition time constant of 10 nanoseconds, a static power consumed by such an output structure would be approximately 210 milliwatts. This condition would effectively defeat the purpose of using complementary IGFET devices to minimize power consumption.
FIG. 1 of the prior art also illustrates the difficulty of having an output voltage of a maximum static high level of V.sub.CC -V.sub.BE. If the output is connected to other complementary IGFET inverters, illustrated as, for example, Q.sub.4 and Q.sub.5, a high output voltage less than V.sub.CC, would turn on all P channel devices, for example, Q.sub.4 if the threshold voltage of Q.sub.4 is less than V.sub.BE. Thus, all interface P channel devices would be slightly on while all N channel interface devices are also substantially on. This condition leads to undesirable static power consumption in other CMOS devices which are interfaced.
In addition to incapatibility with IGFET structures, the buffer of FIG. 1 is also incompatible or causes problems with transistor to transistor logic (TTL). For the buffer Q.sub.1, Q.sub.2, Q.sub.3, to sink TTL logic Q.sub.6, Q.sub.7, Q.sub.8, R.sub.1, R.sub.2, and R.sub.3 having a static load of 10 milliamps and RE of 100 ohms, the output of the buffer would be one volt. This output low voltage is greater than the maximum input voltage of approximately 0.8 volts to the TTL circuit. Thus, the logic low voltage required to provide appropriate current sink is as incompatible with TTL logic as the high level logic is incompatible with complementary IGFET logic.
To reduce the output impedance, the load resistor RE has been replaced by another MOS device as shown in U.S. Pat. No. 3,601,630. Also, the output stage may include a second bipolar transistor in series with the emitter-follower output transistor as illustrated in U.S. Pat. No. 3,609,479. Although both these patents improve the output impedance of the buffer, the circuits still can only provide an output high logic level of V.sub.CC -V.sub.BE. Thus, they no not solve one of the major drawbacks of the prior art buffer circuits.